Electronic substrates are the backbone of all electronic products. Due to the desire for high functionality in a small form factor, multilayer electronic substrates with a high density of circuitry or interconnect (i.e., high density interconnect or HDI), have become increasingly prevalent. The drive to higher circuit layer counts and finer circuit features has been relentless.
The Achilles heel of HDI electronic substrates is the interconnections that must be made in the z-axis direction between circuit layers. Traditionally these interconnections have been made by drilling through a multilayer electronic substrate and then plating the hole barrel with copper to interconnect the layers that the hole contacts. The problem with this type of z-axis interconnection is that the hole takes up space on every layer—including those where an interconnection is not required. As layer counts increase, an additional problem is that it becomes difficult to plate a consistent layer of copper throughout the entire depth of the hole barrel.
In order to overcome these deficiencies, it has become common practice in the industry to fabricate a central core by conventional means and then sequentially add layers of HDI to the outside surfaces of the core. In this method, the sequentially added layers are interconnected by “blind” vias (holes that traverses a dielectric and terminate at a copper pad below) that are located only where needed on each layer and are plated with copper to interconnect to the circuitry directly above and below. The problems with this approach are that the cumulative yield loss for the sequential processing is high, substantial increases in plating capacity are needed for implementation while such capacity requirements are continually increasing, and the via plating operation adds superfluous copper onto each outer circuit layer that is detrimental to the formation of fine circuit features.
One solution to these deficiencies is to install a conductive paste into vias that have been formed in a b-stage dielectric layer prior to lamination to effect z-axis interconnection. This process lends itself to both sequential and parallel fabrication methods. When a parallel process is used, all of the circuit layers can be fabricated in parallel and then joined in a single lamination cycle without the cumulative losses associated with creating an identical multilayer electronic substrate by sequentially laminating multiple layers. This solution also obviates the need for additional plating capacity and does not compromise the formation of fine circuit features. The problems with this method are that the conductive pastes used to form the interconnections are generally not as reliable as the copper-plated vias, and the b-stage dielectric materials typically used to adhere the circuit layers together during lamination are not well-suited to such a process.
Conductive Pastes
Conventional conductive pastes rely on point-to-point contact between metal particles in a polymer binder to effect electrical conduction. This reliance on point-to-point contact is the fundamental basis for the poorer reliability of these materials when compared the continuous metal of a plated via.
The conductivity and reliability of conventional conductive pastes may be sufficient for some applications, and the use of such conductive pastes can be cost-effective. However, in demanding applications, a more robust z-axis interconnection material is needed.
Transient liquid phase sintering (TLPS) pastes overcome the fundamental deficiency of conventional conductive pastes by providing a composition that sinters at lamination temperature to create a metallurgically interconnected metallic network that extends continuously from an overlying copper pad, through the bulk of the TLPS paste, and finally to the underlying copper pad. The use of TLPS compositions as suitable replacements for conventional electrically and/or thermally conductive materials has been used in a diverse assortment of applications, assembly of electronic components, in-plane circuit traces, interconnection of circuit traces on different planes, assembly of unpackaged integrated circuit die onto packaging elements, and the like. Some of the uses for TLPS compositions are described in U.S. Pat. Nos. 6,716,036; 5,980,785; 5,948,533; 5,922,397; 5,853,622; 5,716,663; 5,830,389; 8,221,518; and U.S. Patent Application Publication No. 2011-0171372, which are incorporated by reference herein in their entirety.
Each application presents a specific set of application-specific requirements. TLPS compositions confer an advantage over conventional materials in meeting requirements that include ease of deposition, reduction in manufacturing time and/or complexity, increased circuit density in the resultant article, environmentally stable interfaces, high electrical and/or thermal conductivity, and many others. For use in vias in multilayer electronic substrates the disclosures of U.S. Pat. Nos. 5,948,533 and 8,221,518 and application Publication No. 2011-0171372 are particularly relevant.
TLPS pastes have been demonstrated to form extremely reliable interconnects in multilayer electronic substrates using conventional b-stage lamination adhesives; however, as via sizes become smaller to match shrinking circuit pad size, the use of standard b-stage lamination adhesives not designed for a paste process becomes more problematic.
Bonding Sheets
Typical bonding sheets used for lamination of multilayer electronic substrates are made of thermosetting resins that have been infiltrated into a woven glass mat reinforcement matrix. This type of construction is known as a “prepreg” (woven glass mat pre-impregnated with resin). In HDI electronic substrate applications, where the object is to prepare the smallest and thinnest parts possible, the prepreg is generally selected to have a relatively low glass and a relatively high resin content. Not only do these characteristics facilitate a thin and lightweight part, the low glass density is more amenable to laser ablation to form via holes. This type of configuration is well-suited to the sequential, copper-plated-via process.
Handling of the very thin prepregs used for HDI is difficult. Creating conductive-paste-filled via holes in free-standing prepregs, even with protective coversheets, is particularly difficult to accomplish without damaging or distorting the prepreg. Any distortion is likely to cause misalignment of the vias from one or both of the circuits to be interconnected. In some circumstances, handling issues can be mitigated by tack laminating the prepreg to one of the circuit layers that will be joined by lamination. Nevertheless, other characteristics of HDI prepregs are also detrimental to conductive paste interconnect processes.
In copper-plated-via processes, the bonding sheets used are not subject to thermal processing prior to lamination and high flow is desirable for encapsulating the fine circuit features. Variations in bonding sheet flow characteristics that can be introduced during storage are generally well-tolerated by the process.
In contrast, in paste-filled via processes the bonding sheets are subjected to several intermediate handling steps and often multiple thermal excursions (e.g. tack laminating and extraction of volatiles from the conductive paste), prior to lamination. These intermediate steps can interfere with the ability of the bonding sheet to properly encapsulate and adhere to the circuit layers due to a reduction in flow. Conversely, if the flow of the bonding sheet adhesive is too high, it can migrate to the bottom of the blind via and coat the copper pad, thus preventing connection; it can also flow laterally where it can change the shape or even the position of the via; it can carry a portion of the deposited paste away from the via; and/or it can intermingle with the conductive paste thereby prevent the formation of the conductive pathway. For conductive paste interconnect, unlike copper-plated-via interconnect, flow control of the bonding sheet is critical.
The flow characteristics of standard bonding sheets can be managed by characterization and input of thermal work into the prepreg to achieve optimal flow for specific circumstances. Circuit designs that maximize the amount of copper on mating circuit layers can also be used to limit the amount of lateral flow. However, this is a laborious solution and may not fully address flow issues.
Prepreg bonding sheets characterized as no-flow are available. These materials are generally unaffected by the pre-lamination process steps required for conductive paste vias, and do not cause the interconnect defects associated with high flow resins. The disadvantages of no-flow prepregs are that there is a much more limited selection of materials, it can be more difficult to develop a lamination process using no-flow prepregs that achieves good encapsulation and adhesion for a given part configuration, and available no-flow prepregs are reinforced with woven glass mats.
The woven glass mats used to create prepregs provide good handling and dimensional control characteristics, but they are also a potential source of defects in conductive paste interconnects. The unit size of the glass weave is generally on order of the via hole size. This means that the immediate periphery of each via will vary greatly with regard to resin and glass content. In addition, the lighter glass weaves used for HDI prepregs provide significantly less control over the coefficient of thermal expansion (CTE), while limiting the thinness of the joint that can be achieved. Therefore, the CTE, particularly in the z-axis direction, is relatively high, but the thickness of the glass fabric limits the ability to mitigate any CTE mismatch between the conductive paste and prepreg. Due to the poorer electrical characteristics of glass relative to prepreg resins, a prepreg containing glass must be thicker than one containing resin alone to achieve the necessary dielectric characteristics. Because prepreg resins and glass require different levels of laser energy for ablation, via holes formed in b-stage prepregs will always exhibit some irregularity, which can complicate paste deposition and cause variation in the electrical performance of the conductive paste-filled vias. Finally, adhesion deficiencies between the prepreg resin and glass filaments, such as non-wetting, can create pathways for conductive pastes and/or plating solutions to migrate away from the via structure.
Bonding sheets in which aramid (polymer) fibers replaced the woven glass mats were introduced to alleviate the glass knuckle and lasing issues, but they suffered from high dimensional instability due to moisture absorption, and irregularity of resin penetration into the mat during the infiltration process and have been withdrawn from the market.
Film adhesives have the potential to alleviate all of the issues noted above, but those currently available have a high flow characteristic that tends to sweep conductive vias away.
To take advantage of the cost control, yield improvement, reduction in capital equipment requirements, density capability and design versatility offered by a conductive-paste-filled-via z-axis interconnection strategy for multilayer HDI electronic substrate, what is needed is a building block that provides an electronic substrate substructure bearing an electrically conductive element, that is coupled with an all-polymer bonding film having a portion thereof in a no-flow, b-staged form, with via holes that traverse the thickness of the bonding film, where such via holes are filled with, and/or aligned with bumps formed from a conductive paste that will become a continuous electrical pathway during lamination.